Reaction Timer

---

In a team of three, I developed a reaction timer on an FPGA using VHDL. The timer tracks and stores the three most recent attempts, calculating the max, min, and average times for the user’s reaction.

The system counts down using a series of lights, with the final light turning off at a random interval, signalling the user to press a button as quickly as possible. I have both the report and code for this project, which highlights our approach to digital logic design and timing accuracy.

The report and code is found below for more details on the project.